Paper Special Issue on Synthesis and Verication of Hardware Design a Floorplan Based Methodology for Data-path Synthesis of Sub-micron Asics

SUMMARY As IC fabrication technology enters a deep-submicron region with device feature sizes <0.35m, interconnect becomes the most dominant factor in design of high-speed Application Specic Integrated Circuits (ASICs). This paper proposes a novel methodology for automated data-path synthesis of such circuits and outlines algorithms to support it. In contrast to other approaches, we formulate interconnect area/delay optimizations as high-level synthesis transformations and use them during the synthesis to minimize the impact of wiring on circuit characteristics. Experiments with FIR lter implementations show that such formulation jointly with \on the y" module generation and performance-driven oorplanning provides more than a 30% reduction in wiring delay for deep sub-micron designs. 1. Introduction 1.1 Motivation Due to intensive research on high-level synthesis (HLS) over the last decade, tools[1] capable of mapping behav-ioral specications onto register-transfer level (RTL) structures become an important means of decreasing the design cost and time to market of Application Spe-cic Integrated Circuits (ASICs)[2]. As ASIC complexity exceeds Mega gate level and IC fabrication technology enters a deep sub-micron (<0.3m) region, these tools, however, would be of a little interest if challenges of fabrication technologies are not met. The most signicant challenge evolves from the dominance of interconnect on chip characteristics. With increase in chip density, the average wiring length between the gates increases. The \long" interconnec-tions which earlier were part of the package, due to integration are now placed on a chip. They run between distant parts of the chip and their length is that of a chip edge. Experts [3][4] predict that forthcoming chips will have very long bus lines of length up to 40mm. Since the total length of intrachip connections will grow faster than the number of available gates[5], 70-80% of the future chip area will be occupied by wiring, rather than devices[6]. Furthermore, as device feature sizes are pushed below 0.3m, and gate delays decrease to several picosec-onds, interconnect delays aect circuit behavior. The narrowing of metal lines and interline spacing causes a rapid increase in metal resistance and adjacent wiring capacitance. This implies that densely packed structures require wider metal conductors, which increase the RC constant of the metal lines. For a xed chip size, signal path lengths, as a rule, do not scale. Therefore, the line response time is constant, insensitive to scaling. As result, the gap between the component delays and wiring delays decreases, as feature sizes of the devices become …